The sizes of the microelectronic devices, e.g., transistors, and other active and passive electrical components, continuously scale down in attempts to increase device integration density in integrated circuits that are spaced more closely together. Electrical contacts are fabricated to provide an electrical access to the microelectronic devices built on a wafer. Typically, lithography techniques are used to define the location of contact holes to the devices. As the size of the microelectronic devices and spacing between them decrease, the risk of contact shortings increases. The shorting of the contact may occur, for example, due to misalignments of the contacts, imperfections of the wafer processing operations, and resolution limitations of the patterning and lithography tools. Contact shortings limit the critical dimensions of the devices and the wafer yield.
A typical technique to form self-aligned contacts to source/drain regions of a transistor built on the wafer involves depositing an insulating layer, for example, silicon nitride layer on the transistor. Then the insulating layer is patterned and etched through using conventional photolithographic tools to create contact holes. The contact holes are then filled with a conductive material to form electrical contacts to source/drain regions of the transistor. Due to alignment/registration and other processing imperfections, the contact hole may be created above a gate electrode so that the conductive material may land directly on the gate electrode. Placing the self-aligned contact directly on the gate electrode causes contact-to-gate shorting. The contact-to-gate shorting renders the transistor to be non-operable and results in low wafer yield.
One way to reduce the risk of contact shortings involves developing of lithography alignment techniques that have reduced tolerances. Techniques to reduce lithographic alignment tolerances, however, have typically not scaled at the same rate as techniques to scale the size of microelectronic devices.
Another way to reduce the risk of contact shorting involves reducing of the contact hole size to the devices on the wafer. Reducing the contact hole size, however, may not represent an acceptable approach when forming highly integrated devices because reductions in contact hole size typically lead to substantial and unacceptable increases in contact resistance.
Currently, to reduce the risk of misalignment of the contacts, multiple alignment adjusting operations are performed. Typically, the wafer is subjected to repeating lithography, patterning, etching, and other processing operations until a desired alignment of the contact relative to the contact area of the device is achieved. This approach requires multiple modifications of the wafer that increases the risk of contaminating of the wafer and is time and labor consuming resulting in high manufacturing costs.